锁相环(Phase-Locked Loops)是利用锁相技术对输入时钟信号进行分频或 倍频的电路。这样做的目的是为了降低振荡源频率以减少印制板级的电磁 干扰，使硬件系统...
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All Digital Phase-Locked Loops 全数字锁相环
phase-locked loops system 锁相环路系统
sampled phase-locked loops 取样锁相环
digital phase-locked loops 数字锁相环
digital phase locked loops 数字锁定环
In the digital phase-locked loops, circuit capture time and the performance of anti-noise are contradictory.
在数字锁相环中,环路的捕捉时间和抗噪声性能是一对矛盾。
参考来源 - 基于FPGA技术的相位频率跟踪方法的研究·2,447,543篇论文数据，部分数据来源于NoteExpress
This dissertation presents a study on modeling and circuit design of Charge Pump Phase-Locked Loops.
本文研究了电荷泵锁相环电路的模型和电路设计。
A novel phase detection algorithm that does not need complete period sampling, phase-locked loops or complex electrocircuit hardware was presented in this paper.
本文提出了一种无需整周期采样、无需锁相环和复杂电路硬件的相位检测算法。
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