Moreover, a scan test circuit was proposed. This circuit can implement scan test and high speed build in self test (BIST) for IP core chip tests.
另外,本文还针对IP核投片测试提出一种扫描测试电路结构,能够实现测试芯片的扫描测试和高速内建自测试(BIST)。
It was proved by test that the high-speed detection circuit has better ability and is feasible to apply the high speed detection circuit in FOG with short fiber.
测试结果表明:高速检测电路比普通检测电路具有更高的性能,其应用于短光纤光纤陀螺的方案是可行的。
This paper presents a high speed test generation method specifically for upper large scale combination circuit (ULSCC) and full scan designed circuit.
针对特大规模组合电路和全扫描设计电路提出了一种高速测试生成方法。
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