Then the description of the design of the hardware architecture of the floating-point multiplier and the floating-point adder is made, in which several novel techniques are adopted such as high-speed fixing-point multiplier, fast leading-0-detector-logic and pipeline etc.
随后,论文介绍了浮点乘法器和浮点加减法器的硬件结构设计。 其中采用了高速定点乘法器、快速前导零检测逻辑等几种新技术,并使用了流水线设计思想。
参考来源 - 基于FPGA的高性能32位浮点FFT IP核的开发·2,447,543篇论文数据，部分数据来源于NoteExpress
Through the structure and logical designing, we get a high-speed and effective LOD circuit, which applied in floating-point adder.
我们从LOD的组成结构和逻辑两个方面进行设计，实现了一种快速、高效的LOD电路。
Floating-point adder is one of the basic parts of CPU. Its performance has a direct effect on CPU floating-point processing capacity.
浮点加法器是构成CPU的基本部件之一，其性能优劣将直接影响CPU浮点处理能力。
High-Speed Floating-point Adder is a critical part in the coprocessor, which is attached to the computing basis of floating-point instructions.
浮点加法器是协处理器的核心运算部件，是实现浮点指令各种运算的基础，其设计优化是提高浮点运算速度和精度的关键途径。
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