If the circuit under verification is carved out from the design, the input waveforms to the circuit must be configured to be identical to them when the circuit is embedded in the design.
如果被验证的电路是从设计中勾画出的，那么电路的输入波形必须被配置为与当电路被嵌入到设计中时的一样。
Under pressure of the increase of chip scale and the decrease of timing to market, verification has become the bottleneck of digital IC design.
在芯片规模指数式上升和要求面市时间快速缩短的双重压力下，验证已成为数字集成电路设计的瓶颈。
The traditional verification method can't eliminate all the design error. Therefore, many people tum to various formal verification methods to grantee the correctness of the design under any inputs.
传统的验证手段难以排除所有的设计错误，人们转而求助于各种形式验证方法来保证设计在各种可能输入组合下的正确性。
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