And the selection and design of switch-in module, switch-out module, communication module, clock module, data storage module, keys module and frequency detecting module are also discussed.

论文中还给出了开关量输入、开关量输出、通信模块、时钟电路、数据存储器、按键电路和频率跟踪电路等各功能模块的选择方法和设计原理。

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In the deserializer, parallel data are clocked out by byte clock.

在串并转换接收器中，并行数据在字节时钟的作用下并行输出。

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Data is transmitted out of the FIFO at a transmit clock rate using a transmit address pointer incremented at the transmit clock rate.

数据传输FIFO的，地点为发送时钟使用的传输速率地址指针在发送时钟速度递增。

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