critical delay time 临界延迟时间
critical delay velocity 临界延迟速度
critical delay velocities 临界延迟速度
critical echo delay 临界回声延迟
delay critical 迟延临界
delay critical condition 延迟临界条件
At the situation of high-data-rate, high-parallel, simple algorithm, less states, simple data flow and critical delay, the FPGA can offer a very good solution.
在数据吞吐量大,并行度高,算法比较简单,状态较少,流程比较简单和对时延要求较高的场合,应用FPGA非常适合。
If the beta customer identifies critical usability or missing functionality at this stage, you have a difficult decision: release with the critical defect or delay the release in order to redesign.
如果在此阶段测试客户鉴别出关键的可用性或丢失的功能,那么您就面临困难的决策:发布带有关键缺陷的版本,还是推迟发布重新设计。
The ‘Task Resource Float’ is the amount of delay that can be applied to a task, performed by a Resource, without introducing a delay into another Critical Path task, performed by the same Resource.
任务资源浮动是指用到同一资源时,在不会另一个关键路径任务延迟的情况下,一个任务可以被延迟的时间。
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