Thus, it is important to study protocols and implementation of system bus to hide memory latency and increase memory access rate.

因此研究系统总线协议及其实现技术对于隐藏访存延迟和提高访存速度具有重要意义。

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Off-chip memory latency is mainly determined by DRAM latency, and memory bandwidth is determined by data transfer rate through the memory bus.

片外存储系统的访存延迟主要由DRAM延迟决定，带宽则是由内存总线的数据传输率所决定。

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Residing directly on the PCIe bus, this new addition to the Vector Series provides lower latency to data, faster file transfers and boot-ups, expanded storage capacities, and an even quicker, more responsive experience over the already blazing fast SATA III-based Vector SSDs.

ENGADGET: OCZ demos Vector SSD in even speedier PCI Express form for the pros