TLB cache entry reuse (cache hit) equates to quicker address translation and subsequently faster access to physical memory.
tlb缓存条目重用(缓存命中)意味着更快的地址转换,还意味着对物理内存的更快的访问。
Pacifica also amends address translation with host and guest memory management unit (MMU) tables.
Pacifica还可以使用宿主和客户内存管理单元(MMU)表来进行地址转换。
To help address translation, operating systems cache the translated memory addresses by a process called Translation Look-aside Buffering (TLB).
为了帮助地址转换,操作系统通过一个叫做转换后援缓冲(Translation Look-aside Buffering,TLB) 的进程来缓存已转换的内存地址。
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