...乘法器;加法树 [gap=658] words : finite impulse response filter ;very large scale IC ;BOOTH multiplier ;adder array tree ...
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The timing requirements for PE structure and the adder array for adder tree structure to optimize performance of design are studied and used.
研究了并利用PE(处理单元)结构时序约束和加法树结构的加法阵列优化设计性能。
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