本文分析了VLSI阵列处理器的算法和结构，并介绍了把算法映射为阵列结构的基本方法。

In this paper, we give an introduction to the algorithms and architectures of VLSI array processors. We also introduce a basic approach to map the algorithms onto array structures.

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该结构将波前控制算法分为递归运算和卷积运算两部分后，采用规范映射方法将其分别映射到脉动阵列，再将两个阵列链接以实现单路的波前控制运算。

This structure divides wavefront control calculation into recursive algorithm and convolution algorithm, and maps them to respectively systolic array by using canonical mapping method.

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采用基于BP神经网络整定的PID控制策略以减弱系统的耦合影响，并给出了其控制算法在FPGA上实现的方法，包括脉动阵列算法映射、数据表示及精度和运算部件设计。

A control strategy based on BP-PID was introduced to decouple the looper system by using FPGA, which includeds systolic mapping, data representation and precision, and computation components design.

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