图 3-3 载波同步与载波不同步示意图 3.3 采样时钟同步偏差 采样时钟同步(Sample Clock Synchronization)是由收发两端的 A/D、 D/A 转换器的抽样频率是否相同所决定的。
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为了能在异步控制网络上实现采样同步,可采用时钟同步方法。
Using the clock synchronization, synchronous sampling could be realized on an asynchronous control network.
该系统采用了片同步技术实现了采样后高速数字信号的可靠锁存,采用高精度的时钟管理芯片和设计合理的时钟路径对时钟抖动做了严格控制。
The Chip-Sync technology has been used to ensure the latch of high-speed signal, and we use high accuracy clock management chips and design reasonable clock way to strict control the clock jitter.
该方法是一种基于信号采样时钟速率的全数字化处理过程,其同步精度可达到信号采样间隔的1%以上,且便于FPGA或DSP实现。
The method is a fully-digitized process at the sampling clock rate, so that it can be conveniently implemented by FPGA or DSP, whose synchronization precision can reach 1% of the sampling interval.
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