在计算机中普遍运用,异或(xrl)的逻辑符号一般用xrl,也有用⊕的: 真⊕假=真 假⊕真=真 假⊕假=假 真⊕真=假 或者为: True ⊕ False = True False ⊕ True = True False ⊕ False = False True ⊕ True = False
此方案完全采用逻辑异或运算,因此编码和解码速度快。
The logical exclusion OR operation are fully applied to the scheme so coding and decoding speed is quick.
在试验中,他们构建了一个DNA版本的“异或”逻辑门,当两个输入端中有一个有输入时,产生输出;但当两个输入端都有或都没有输入时,就不会产生输出。
In tests, they modeled a DNA version of an XOR logic gate that generates an output when one of two inputs is present, but not when both or neither is present.
这种电路充分利用与电路、或电路、异或电路的功能,把一个较为复杂的判断电路,变成简单的逻辑组合电路。
The circuit makes full ues of functions of and circuit, or circuit and exclusive or circuit, which turns the more complex judging circuit into simple combinatory logic circuit.
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