该设计采用可编程逻辑器件，VHDL硬件描述语言为输入工具，接口简单，可靠性高，具有一定的实用价值。
The programmable logic device and VHDL is used as input tools, which have simple software interface, good reliability and practical value.
CPU内核采用VHDL硬件描述语言输入，结合流行的EDA设计、综合、仿真工具，最后在FPGA上实现该内核。
The reference CPU core use VHDL language input, make logic synthesis and simulation through the popular EDA tools, then it was implemented in FPGA.
本文利用VHDL硬件描述语言设计了一种SVPWM信号发生器，该信号发生器不仅成功实现了输入时间信号到SVPWM触发信号的转换，而且具有良好的抗干扰能力。
In this paper, a SVPWM signal generator is designed with VHDL. This signal generator can transform time signal into SVPWM trigger signal successfully with good anti-jamming capability.
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