...n.com豆丁网 -bias cascade mirrior; Voltage-follower 1 引言 CMOS 电荷泵锁相环电路（Charge Pump Phase-locked Loop, CPPLL）具有高速、低功耗、 低抖动、低成本等优点，在频率合成、时钟恢复等电路中被广泛采用。
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...计 - docin.com豆丁网 -bias cascade mirrior; Voltage-follower 1 引言 CMOS 电荷泵锁相环电路（Charge Pump Phase-locked Loop, CPPLL）具有高速、低功耗、 低抖动、低成本等优点，在频率合成、时钟恢复等电路中被广泛采用。
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本文研究了电荷泵锁相环电路的模型和电路设计。
This dissertation presents a study on modeling and circuit design of Charge Pump Phase-Locked Loops.
文章在深入分析电荷泵锁相环设计理论的基础上，根据DSP芯片对锁相环的具体应用要求，确定了锁相环的总体电路结构和各项性能参数。
Based on the analysis of the theory of CPPLL and application requirements in the DSP, the structure and the performance specifications of the PLL are defined, and then the subcircuits are designed.
本文的目的是研究目前应用最广的电荷泵锁相环的噪声特性以寻找减小环路噪声的电路架构。
The objective of the thesis is to explore the noise sources in PLL and find the proper circuit structures to reduce the noise effects.
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