如果您没有将工作平台上的时钟和所有在测系统上的时钟进行同步，那么报告中的资源计数器将显示不准确(就时间而论)。
If you do not synchronize the clocks on the workbench and on all of the systems under test, resource counters are displayed inaccurately (with respect to time) in the reports.
每当计数器被时钟脉冲触发一次时，计数器输出的二进制数便累减1。
The counter output, which represents a binary number, decreases by 1 any time the counter is triggered by a pulse .
该文从消除时钟信号冗余跳变而致的无效功耗的要求出发，提出了应用并行技术和流水线技术，实现基于RTL级的双边沿触发计数器的设计。
To erase the bootless power dissipation of the redundant leap of the clock, this paper proposes the RTL design of double edge triggered counter using parallelism and pipeline technique.
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