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In this dissertation, we mainly discussed the design method of ternary ECL sequential circuits. The new clock structure—parallel-or clock structure was presented to design different types of latches and triggers.
本文主要讨论了三值ECL时序电路的设计方法,提出了ECL时序电路中一种新型的时钟结构——并联取小时钟结构,并设计了基于此种时钟结构的多种锁存器及寄存器结构。
参考来源 - 基于并联取小时钟结构的ECL时序电路设计研究·2,447,543篇论文数据，部分数据来源于NoteExpress
此后，介绍了低功耗设计方法，本设计主要采用门控时钟结构来降低功耗。
Then the methods of low power design are introduced, and the clock gated is used in this design.
最后，英特尔计划使其全线产品加快向多核体系结构转换，同时业内分析人士期望处理器时钟速度可以在未来几年内趋于平稳。
Finally, Intel has plans to quickly transition to multi-core architecture across all of its product lines and most industry watchers expect processor clock speeds to level off in the years ahead.
系统采用双时钟设计结构，使得奇校验电路结构简单、易实现。
The system is of double clock design structure which makes the odd verifying circuit structure simple and easily effected.
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