差分时钟延迟匹配技术通过对两路AD的采样时钟进行相位调整，实现了两路AD的等间隔采样。

The difference clock delay match technology adjusts the two channel AD analog clock phase and implements the two way AD uniformly-space sampling.

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整个设计采用VHDL语言描述，经过逻辑优化，该显示控制器有着比同类控制器占用资源少、时钟延迟小等优点。

The whole design is described in VHDL. By logic optimization, the controller has an advantage of less resource utilization and less clock delay compared with other similar controllers.

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工作时间并不是仅仅由时钟决定，而且通过工作延迟，孩子的数量，返回时间的耽搁和其他情况所决定。

Hours are not only determined by the clock, but by tardiness, the number of children, lateness of returning, and other considerations.

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