本文提出了基于FPGA技术实现数字复接系统的设计方案,并介绍了有代表性的较简单的四路同步复接器系统总体设计。
This paper puts forward a design method of digital multiplex system with FPGA , and introduces the whole system of four bits synchronous multiplexing .
在复分接系统中,如同步数字系列(SDH),定时处理占有重要地位。
In multiplex and demultiplex systems such as Synchronous Digital Hierarchy (SDH), timing processing is very important to system performance.
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