在FPGA的情况下，所使用的元胞块数量也会在很大程度上影响布线后的最终延迟，因为大多数延迟是由存在的可编程互连所引起的布线延迟。
In the case of FPGAs, the number of blocks used will also greatly influence the final delay after routing because most of the delays is the wiring delays due to the programmable interconnect existed.
两线 串行接口，实现输出会被强制平仓，调整和上升和下降，在可编程的摆率与测序的延迟时间。 输入和输出电压，以及输入和输出电流和温度是可读的。
The two-wire serial interface enables outputs to be margined, tuned and ramped up and down at programmable slew rates with sequenced delay times.
介绍了复杂可编程器件(CPLD)和可编程数字延迟线(AD95 0 1)在系统中的应用。
The application of complex programmable logic device (CPLD) and digital programmable delay line AD9501 in the system is described.
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