简述了FPGA在高速位误码率测试仪中的应用，对误码率测试仪的结构，及其FPGA实现进行了详细的介绍。
The structure of the high-speed BER testing instrument is introduced. The application of FPGA in the instrument and the realization of FPGA are expounded.
其次，分析了位定时抖动对误码率的影响。
Secondly, the effects of the jitter of bit-timing on error performances are discussed.
位同步信号本身的抖动、错位会直接降低通信设备的抗干扰性能，使误码率上升，甚至会使传输遭到完全破坏。
Jitter and misplace of the bit synchronization signal will reduce the anti-interference performances of communication equipment directly, also increase bit error probabaility.
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