∑ΔADC由两个主要的部件构成:一个模拟∑Δmodulator(调制器)和一个数字抽取滤波器(digital decimation filter)。数字抽取滤波器的主要作用是滤除可能引起混迭的带外噪声,其次,它能够将前级调制器过采样的高速率数据降低
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The digital decimation filter taking the important constituent in the Delta-Sigma Analog-to-Digital converter is realized by the multistage structure.
数字抽取滤波器是它的重要组成部分，通常采用多级结构来实现。
According to the character of FPGA, the FIR digital decimation filter is implemented via using distribution algorithms which are based on the technique of looking up table.
根据FPGA芯片的特点，FIR数字抽取滤波器采用分布式算法来实现，这种方法实现的基础是查找表。
In this paper, the high decimation ratio of digital down converter is studied and the multi-stage decimation algorithm is especially analyzed based on CIC filter, CFIR filter and RRC filter.
研究了高倍抽取的数字下变频设计，重点分析了基于级联积分梳状滤波器、级联补偿滤波器、级联根升余弦滤波器的多级抽样频率算法。
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