layout-designs of integrated circuit 积体电路之电路布局
For detecting the potential common errors of integrated circuit designs quickly and efficiently, this paper introduces a novel error defection approach based on static analysis.
为快速有效地对集成电路设计中潜在的常见错误进行检测，提出一种基于静态分析的错误检测方法。
Verification is the bottleneck of more and more complex integrated circuit designs, and doing verification directly on register transfer level (RTL) is a promising solution.
验证是当前越来越复杂的集成电路设计中的瓶颈，在寄存器传输级（RTL）直接做验证是目前比较有效的一种途径。
The website offers knowledge of patents, trademarks, copyright, and industrial designs, integrated circuit topographies.
该网站提供了关于专利、商标、版权、工业设计、集成电路设计的知识。
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