... Clock Frequency):50 MHz • 处理器总线时钟频率(Processor Bus Clock Frequency):50 MHz • 调试接口(Debug Interface):On-chip H/W debug module • 本地数据指令存储空间(Local Data and Instruction Memory):8 KB • Cache 使能(Cache Enabl...
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Remote Debug Interface 远程调试接口
embedded debug interface 嵌入式调试接口
Microprocessor Debug Interface 微处理器调试接口
Debug Interface Access SDK 调试接口访问
To enhance the stability of the system, design a lot of decoupling and bypass capacitors in hardware circuit. And the JTAG debug interface is designed for convenient debugging.
在硬件电路设计中,大量采用了性能较好的去耦和旁路电容来加强系统的稳定性,并为了调试方便设计了JTAG接口。
Agent design and management with a redesigned agent interface and enhanced agent properties along with the ability to attach and debug agents running on the server.
代理设计和管理,重新设计了代理界面,增强了代理的属性,能够附加和调试在服务器上运行的代理。
Suppose you want to debug the user interface creation in HelloWorld.
假设您想调试HelloWorld中的用户界面创建。
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