Serial Clock Line 串行时钟线 ; 一根为串行时钟线
word clock line 时脉线
bit clock line 位元时脉线
Keyboard clock line failure 键盘时钟线路出现故障
Keyboard d clock line failure 键盘时钟线路出现故障
Keylap board clock line failure 键盘时钟线路出现故障
clock source line 时钟设定
line clock interface board 外基准输入接口板
Line clock 行时钟 ; 线性时钟
The host changes the data line only when the Clock line is low, and data is read by the device when Clock is high.
只有当时钟线为低的时候，主机才可以改变数据线(也就是将数据写入到数据线)。数据将在时钟为高电平的时候被设备读龋。
The host has ultimate control over the bus and may inhibit communication at any time by pulling the Clock line low.
主机对总线有最高的控制权，在任何时候通过将时钟线拉低就可以禁止通信。
When the keyboard or mouse wants to send information, it first checks the Clock line to make sure it's at a high logic level.
当键盘或者鼠标想发送数据时，它首先必须检查时钟线，确认它处于高电平。
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