Building the transition relation of sequential logic circuit is one of the key technologies for applying model checking method to verify the sequential logic circuit.
有效地建立和表示时序逻辑电路的状态转移关系是应用模型检查方法验证时序逻辑电路的关键技术之一。
CMOS symmetrical three-valued ternary logic circuit was designed and fabricated, based on the information associated with symmetrical ternary logic combined with CMOS circuit processing features.
根据有关对称三进制逻辑的资料,结合CMOS电路生产工艺特点,设计并试制了对称三值逻辑CMOS系列电路。
This paper review elementary theory for new logic circuit with ROM memory array, and provide design method for two practical array logic circuit.
本文论述用ROM的存贮阵列构成新颖的组合逻辑电路和时序逻辑电路的基本原理,并给出两个实际的阵列式逻辑电路的设计方法。
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