As an external interface of the processor, system bus component affects the efficiency of memory system directly.
作为处理器的片外接口，系统总线部件直接影响着存储系统的效能。
The bus and the processor core often run in different clock frequencies, so their interface signals belong to different clock domains.
总线时钟与处理器内核时钟频率不同，因此总线部件与处理器内核间的接口信号需要进行时钟域转换。
Logic for interface to the back-side bus for accesses to the internal unified level two processor cache.
访问内部统一二级处理器缓存的后端总线接口逻辑。
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