这样的电路安排能够非常有效的减小栅极至屏级间电容。
Such an arrangement would effectively nullify the grid-to-plate capacitance. The following circuit shows how this can be realized.
但最根本的应该是在印刷电路板设计、元器件布置和连接线的安排上下功夫,抑制共模骚扰源的产生。
But most attention should be put on the PCB design, elements position and line connection, which can suppress the source of the common mode disturbance.
该电路是不是推挽安排,只发出荧光的发光在时间周期,当晶体管处于关闭状态。
This circuit is not a push-pull arrangement and the EL only fluoresces during the time-period when the transistor is turned off.
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