介绍了利用VHDL硬件描述语言结合FPGA可编程器件进行数字钟的设计，并通过数码管驱动电路动态显示计时结果。
The paper introduces the design of digital clock based on FPGA and VHDL, the time of clock can be displayed with the digital driving circuit.
可直接驱动液晶显示器，增加适当的驱动电路可采用数码管显示。
It is possible to drive liquidcrystal display directly, and to use the digital tube demonstration by increasing the suitable actuation electric circuit.
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