介绍了利用VHDL硬件描述语言结合FPGA可编程器件进行数字钟的设计，并通过数码管驱动电路动态显示计时结果。
The paper introduces the design of digital clock based on FPGA and VHDL, the time of clock can be displayed with the digital driving circuit.
随着PLD功能的日益强大，数字电路设计已经进入全面革新的时代，HDL语言正是这个时代有力的工具。
With the function of PLD becoming increasingly powerful, the innovation age of the digital circuit design has arrived, in which HDL language is a powerful tool.
对数据库中的数据研究和分析，利用统一建模语言(uml)分析和设计数字河道信息管理系统。
Through the research and analysis of data in the database, unified modeling language (UML) is used to analyze and design the digital river information management system.
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