... Signal system 号志系统 Signal timing design 信号时序设计；号志时制设计；号志时段设计 Signal Timing Plans 号志时制计画 ...
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采用新型的GTL总线收发器、时钟相位调节和组合式匹配等技术措施，解决了总线设计的驱动、时序和信号完整性问题。
The problems of backplane bus design, such as the driver, timing and signal integrate, have solved by using the GTL transceivers, phase adjustment of the clock and combined match techniques.
对其中的关键信号处理流程如载波恢复、时序恢复等提供了设计和性能分析。
There are illustrations for designing and analysis for performance of important signal processing steps such as carrier recovery and timing recovery etc.
设计了二进制树型拓扑结构传播统一的系统时钟和触发信号，采用CPLD提供传感器间的精确时序和同步。
A binary tree routing topology is designed for propagating the system clock and trigger signal and the accurate timing and synchronization between sensors are provided by CPLD.
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