文章介绍利用多时钟产生存储器接口控制信号的方法，为建立软核仿真平台提供了一个新的途径。
This paper presents a way to generate control signals of the interface of memory using many clocks, and offers a new way for setting up the soft-core simulation platform.
系统以ARM微处理器和FIFO存储器为核心，利用可编程逻辑器件实现对整个底层数据采集系统的逻辑控制，并给出了时序控制部分的仿真波形。
The system controls the logic of the data acquisition board by programmable logic device (PLD) with the center of the ARM microcontroller and FIFO memory and provides the simulate waveforms.
实际的仿真和测试结果表明，在人工耳蜗应用当中，恰当地结合使用这两种方法，可以使DS P中存储器的功耗降低50%以上。
Actual simulation and measured results show that, proper joint application of these two methods can reduce the power dissipation of the memory in the DSP by more than 50%.
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