在脉冲发生器输出端后加一级驱动电路,再接入计数器的时钟脉冲源输入端,可有效地避免通常发生在实验过程中计数器不规则的跳变。
To use the way of put a driven circuit behind the pulser, lead through the input of count clock pulse, can avoid the irregular date on the counter during experiment effectively.
传统的数字比较器采用门级设计技术,电路结构不规则,不利于大规模集成电路的设计。
The traditional magnitude comparator is based on gate-level techniques and not suitable for VLSI design.
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