同步捕获后则通过锁相环技术跟踪长突发的同步变化。
After attaining synchronization, the phase offset due to frequency offset estimation error is tracked with a phase locked loop.
特种的传导电缆和特殊的锁相环技术使高度信号更精准；
The conduction of special cable and special phase lock loop technology makes high signal more accurate;
介绍了一类基于双向输入型鉴相器锁相环技术的时钟恢复系统。
The paper introduces a kind of clock recovery system based on phase-locked loop with bi-directly incident phase-comparator.
采用了硬件锁相环技术，可更加有效实现同步采样，提高了采样精度。
Application of the hardware PLL technology can achieve the synchronous sampling more effectively and help improve the sampling accuracy.
运用锁相环技术使采样频率同步跟踪信号频率，提高采样数据计算的准确性。
The use of phase-locked loop technology makes the sampling frequency synchronously follow the signal frequency and improves the calculation accuracy of sampling data.
研究了软件锁相环技术在陀螺用无位置传感器无刷直流电机稳速控制系统中的应用。
The software phase-locked loop (SPLL) technology in the steady speed control of permanent magnet brushless DC motor (BLDCM) in gyro was discussed.
设计具体的锁相环电路，并建立利用锁相环技术检测荧光寿命的荧光温度传感器系统。
The fluorescence thermometry system in which the fluorescence lifetime is detected by phase-locked loop is established, and the specific phase-locked loop circuit is designed.
采用高精度的直接数字频率合成（DDS）和数字锁相环技术，实现了高频率跟踪精度。
DDS and digital phrase-lock technology have been applied in FPGA to improve the accuracy of frequency tracking.
采用锁相环技术实现高精度电机调速，并结合蓝牙通讯技术，使小车达到系统的理想要求。
The PLL technique is used to realize the precision DC motor timing. By employing bluetooth communication…
采用锁相环技术实现高精度电机调速，并结合蓝牙通讯技术，使小车达到系统的理想要求。
The PLL technique is used to realize the precision DC motor timing. By employing bluetooth communication technique,...
本文研究了三相电压源型逆变器实现并网所采用的控制方法，包括空间矢量调制法和锁相环技术。
A method of the three phase voltage-source inverter connecting to the grid is studied, which consists of space vector pulse width modulation and phase-locking method.
随后，本文详细讨论了并网过程中的软件锁相环技术，对锁相环电路的组成、工作原理进行了研究。
Subsequently, the detailed discussion of the software phase-locked loop technology and network process, the composition of the phase-locked loop circuit, the working principle of the study.
随着时钟频率的不断提高，微处理器的性能受锁相环的影响越来越大，锁相环技术已经成为当代微处理器的核心技术之一。
The higher the clock frequency is, the more PLL influences the performance of microprocessors. PLL technique has been one of the core techniques in modern microprocessor design.
提出了一种以复杂可编程逻辑器件（CPLD）和锁相环技术为核心的新型通用数字触发器，对其硬件电路和软件设计进行了详细分析。
To aim at the defect of the simulate trigger and the digital trigger with microcomputer, a new universal digital trigger based on CPLD and PLL is introduced.
实践表明：利用一种改进的FFT校频技术对载波频偏进行一次校频，能使载波频偏快速落入锁相环快捕带内。
It has been proved that an improved FFT frequency correction technology, which makes carrier frequency deviation come into fast capture bandwidth quickly, is presented to correct frequency.
最后分别对改进的FFT校频技术及锁相环进行了仿真分析，结果表明该方法在低信噪比下仍具有良好的性能。
Finally, a simulation analysis for the improved FFT frequency correction technology and phase-lock loop is maked, the result shows that the method also has a good performance in the low SNR situation.
介绍了锁相环(PLL)技术和直接数字式频率合成(DDS)技术的基本工作原理，给出了一种提高DDS输出频率精度及减小其相位截断误差的方法。
This paper introduces the theory of the phase-locked loop (PLL) and the direct digital synthesis (DDS), a method to improve the precision of DDS and reduce its phase truncation error is also given.
本文给出了一种采用自偏置技术的低抖动延迟锁相环，可应用于高频时钟产生电路。
In this paper, a low-jitter process-independent DLL(delay locked loop) based on self-biased techniques is presented.
以数字延迟锁相环为基础，并采用数模混合技术，实现了带电源控制的数字延迟锁相环。
Based on digital delay-locked loop, the mix signal technique is used to implement the digital delay locked loop with the resource control technique.
利用锁相环的倍频、分频等频率合成技术，可以获得多频率、高稳定的振荡信号输出。
Using PLL synthesis technology such as frequency multiplication and frequency division, may obtain the multi-frequencies, the high stable oscillator signal output.
第四章探讨了运用可编程技术设计数字锁相环和数字倍频器的相关问题，为以后电路设计拓展更多的方法。
The chapter 4 discuss some question of the circuit using programmable device like digital phase locked loop and digital frequency multiplier, it can increase the way of circuit design.
本文研究了高动态GPS／BD-2软件接收机关键技术并设计实现了其验证平台，其中研究的重点是锁相环及快速捕获方法。
This paper designs and implements key technology of high dynamic GPS/BD-2 receiver and the verification platform, with main researches on PLL and rapid acquisition.
重点研究了基于FPGA的全数字锁相环频率跟踪技术和数字化SPWM实现技术。
All digital Phase-Locked Loop frequency tracking and digital SPWM realization technology based on FPGA are emphasized in the research.
重点研究了基于FPGA的全数字锁相环频率跟踪技术和数字化SPWM实现技术。
All digital Phase-Locked Loop frequency tracking and digital SPWM realization technology based on FPGA are emphasized in the research.
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