通过控制一个N位累加器累加，取其最高位，即可得到可编程时钟源。
Through controlling an N-bit accumulator and then get its highest bit to generate the programmable clock.
其思想是按照外部时钟的步调在更短的时间内完成一项工作，即便要以更复杂的硬件和编程为代价也在所不惜。
The idea is to finish a job in a shorter time as measured by an external clock, even if at the cost of more hardware and programming complexity.
让我们把时钟往回调一小段，你会发现这样的观点似曾相识，当初在质疑面向对象编程时，就发出过类似奇怪的声音。
If you go back in time a little, you'll discover that this argument sounds curiously similar to the one used to voice initial skepticism toward object-oriented programming.
着重阐述了软件设计中数据采集、显示、存储、时钟控制、RS485通信的编程思路。
It emphasized the programming thoughts of data collection, display, storage, clock control and RS485 communication in software design.
本文介绍了DS1302日历时钟芯片的工作原理和编程方法。
This paper introduces the work principle and program method of DS1302 trickle charge timekeeping chip.
用复杂可编程芯片(CPLD)实现，并用于雷达数字光纤通信系统的信道编码，提高了时钟提取的性能。
The scheme can be implemented by using the CPLD chip, and used for the channel coder in a radar digital optic-fiber communication system and improving the features of clock extraction.
该文介绍了如何利用可编程控制器的日历时钟功能，对一灯饰控制系统进行自动控制，从软件、硬件两个方面介绍了具体实现的方法。
The paper presents a lighting decoration control system, in which clocking function of PLC is used and automatic timing control of lighting decoration system may be realized.
该系统还能实现单片机与PC机的串行通信和编程的下载、软件设计的时钟显示。
Here the whole system can realize serial communication of Single Chip Micyoco and machine PC, the download of programming, the display of the clock which is designed by software.
介绍了可编程控制器机内时钟的设定及时间控制的方法，给出了编程实例。
This paper passes on clock setting and time controlling methods on PLC, and gives program examples.
在各个实施例中，该方法可包括配置不同的可编程测试时钟控制器来基本上并行地测试不同域。
In various embodiments, the method can include configuring different programmable test clock controllers to test different domains substantially in parallel.
输出时钟信号还具有可编程的相移和占空比调节等高级时钟变化功能。
The output clock signal has advanced clock shift ability such that the phase shift and duty cycle are programmable.
本实用新型公开一种时钟同步倍频电路，尤其涉及电路设计和可编程逻 辑器件设计中时钟倍频电路。
The utility model discloses a clock synchronized frequency multiplication circuit, in particular relating to clock synchronized frequency multiplication circuit in circuit design and PLC design.
一个极宽的可编程频率范围允许时钟以一个1ms至9.5小时的周期运作。
An extremely wide programmable frequency range allows the clock to operate with a period from 1ms to 9.5 hours.
一个极宽的可编程频率范围允许时钟以一个1ms至9.5小时的周期运作。
An extremely wide programmable frequency range allows the clock to operate with a period from 1ms to 9.5 hours.
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