第一开关电路耦 接至电平转换器，并在第三晶体管导通时，关闭第四晶体管。
The first switch circuit is coupled to the electrical level translator and turns off the fourth transistor when the third transistor is turned on.
而第二开关电路耦接至电平转换器，并在第一晶体管导通时，关闭第二晶体管。
While the second switch circuit is coupled to the electrical level translator and turns off the second transistor when the first transistor is turned on.
介绍了IRIG-B码对时的概念、IRIG-B码对时模块的组成，其组成部分包括微处理器、电平转换器件、光耦隔离器。
The paper introduces the time synchronization conception of the IRIG-B format code and its module constructions which include microprocessor, level converter and optically coupled isolator.
“满刻度”是指转换器可能达到“数字过载”之前的最大可编码模拟信号电平。
"Full scale" refers to the converter could reach the "digital overload" maximum before the encoding analog signal levels.
另一方面，为了兼容其他那些工作输入信号电压不为0的器件，如模数-数模转换器，信号电平也许要做平移。
On the other hand, the signal may require level shifting in order to be compatible with the input of other devices (such as ADCs) that are not designed to operate at 0v input.
另一方面，为了兼容其他那些工作输入信号电压不为0的器件，如模数-数模转换器，信号电平也许要做平移。
On the other hand, the signal may require level shifting in order to be compatible with the input of other devices (such as ADCs) that are not designed to operate at 0v input.
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