因此，合理规划北二环路信号控制方式能给道里、道外区带来巨大经济和社会效益。
So to design a reasonable line control program of the second ring road will bring a great economic and societal benefit.
在信号传感器或信号转换器遇到接地的输入或输出信号时，电流环路信号隔离器减少现场测量难题。
DEVAR current loop signal isolators reduce problems found in field measurements when signal transmitters or converters encounter both input and output signals that may be grounded.
该锁相环由计算频率误差、更新环路中间变量、输出控制信号组成。
The SPLL consists of calculation frequency error, updating loop middle variable, and output control signal.
在接地信号源RSE测量系统中引入接地环路会导致所测的信号源电压值产生误差。
The hazard of using an RSE system with a grounded signal source is the introduction of ground loops, a possible source of measurement error.
相位相干通信系统中，通常采用锁相环路来产生相干参考信号。
In phase-coherent communication system, phase-locked loop is always used to yield coherent reference signal.
较长的本地环路需求某种形式的放大机制以维持信号强度。
Longer loop lengths require some form of ampli? Cation in order to maintain signal strength.
环路滤波器的作用就是滤除从PFD&CP出来的电压中的高频成分，从而纯化VCO的输出信号。
The function of a loop filter is to filter high-frequency signal out of the output voltage from PFD and CP, thus the output signal from VCO will be purified.
基于低功耗设计考虑，调制器采用有源-无源混合型环路滤波器，并通过离散时间微分技术移除信号求和模块。
Upon the low power design consideration, a hybrid active-passive loop filter is employed and the signal summing block is removed by using discrete-time differentiation technique.
并分析论证了在一定条件下emc与环路面积、信号完整性之间的关系。
Also this paper explains the relations among EMC, Signal Integrity and Circle Area with theory and experiments based on some cases.
低阶锁相环跟踪频率斜升信号时产生的稳态相差致使环路失锁，接收机无法锁定载波信号。
Due to steady phase error, low-order PLL has a trouble in tracking frequency ramp signals, so that the receiver cannot lock carrier signals.
最后将码跟踪环与载波跟踪环路耦合对采集的GPS信号闭环跟踪，并对不同信号强度下的跟踪结果进行对比分析。
Finally, code loop and carrier loop are coupled together to track GPS signal in close loop, and analyze of different performances on track loop under different signal intensity is given.
本文讨论了采用锁相环路作为本振信号的混频器对本振锁相环路的影响。
This paper discusses the influence of mixer on the phase lock-loop (PLL) circuit of a local oscillator. In mixer, local signal is produced by the PLL circuit.
在接收机的设计中，较多地采用了数字化技术，使用数字信号处理芯片TMS320C 25完成主要的环路运算工作。
The digital techniques are widely used in the receiver design and the main loop program is executed in DSP TMS320C25.
环路滤波器中的有源和无源器件均有噪声产生，此类噪声会叠加在输出信号上，从而恶化输出信号的相位噪声。
Noise which comes from both active and passive circuit element in loop filter will deteriorate phase noise of output signal.
锁相环路是完成两个电信号相位同步的反馈控制系统，适宜于变流装置的同步触发电路之中。
The phase lock loop is a feedback control system that makes two telecommunication signals' phase synchronization, suitable to the synchronous trigger circuit of the convertor device.
整数频率合成器输出信号的频率是参考信号频率的整数倍，环路的频率分辨率为参考频率。
The output signal frequency of integer frequency synthesizer is the integral multiple of reference signal frequency, Loop frequency resolution is the reference frequency.
为此提出了基于D触发器环路的相控阵信号发生技术和基于时分复用数模转换器（DAC）的相控阵信号发生技术。
Two approaches are developed:one based on a D flip-flop loop and the other based on a time-division multiplexing digital-to-analog converter (DAC).
针对这一问题，该文将OQPSK信号的平方谱与载波同步环路相结合设计了改进算法。
To resolve this problem, this paper designs an improved algorithm based on the power spectrum of OQPSK signal and the feedback structure.
针对这一问题，该文将OQPSK信号的平方谱与载波同步环路相结合设计了改进算法。
To resolve this problem, this paper designs an improved algorithm based on the power spectrum of OQPSK signal and the feedback structure.
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