您还需要知道J VM能否确定主机处理器的体系结构，以使得JIT编译器可以为那个体系结构生成正确的指令集。
You also need to know whether the JVM correctly determines host processor architecture so that the JIT compiler can produce the correct set of instructions for that architecture.
为了生成主机处理器的正确的指令集，JIT编译器需要明确地确定底层的处理器的体系结构类型。
In order to generate the exact set of the host processor's instructions, the JIT compiler needs to precisely determine the architecture type of the underlying processor.
它使用堆栈体系结构，这意味着在使用指令操作数之前要先将它们装入内部堆栈。
It USES a stack architecture, meaning instruction operands are loaded to an internal stack before they're used.
另外一种主要的处理器体系结构CISC (x86处理器就是一种流行的CISC指令集)几乎允许在每条指令中进行内存访问。
The other main type of processor architecture, CISC (the x86 processor being a popular CISC instruction set), allows for memory access in nearly every instruction.
并行程序的性能与计算机体系结构密切相关，不但取决于CPU，还与系统架构、指令结构、存储部件的存取速度等因素有关。
The performance of parallel program is closely related to computer architecture, besides CPU, including system framework, instruction structure and access speed of storage unit.
计算机内部指令的具体驱动形式与计算机体系结构的具体组成是密切相关的。
There is close relationship between the driven-mode of the, internal instruction and the organization of the Computer architecture.
芯片使用可重构体系结构和超长指令字(VLIW)，优化了高复杂度函数。
The chip USES a reconfigurable architecture and very long instruction words (VLIW) to optimize the complex functions.
本文将从算法级并行处理、指令级并行处理与进程级并行处理等三个方面讨论嵌入式RISC体系结构的设计问题。
The design problem of an embedded RISC architecture in parallel processing of algorithm level, instruction level and process level is discussed in this paper.
为加速循环程序执行，提出了固定指令多数据流计算模型，并设计了一个单芯片阵列处理器体系结构。
We put forward a technology named fixed instruction multiple data in order to accelerate the loop, and design a chip-multiprocessors architecture.
某些体系结构不允许执行指令指向目标指令的地址，真正的程序员才不管这种小小的限制。
Some candyass architectures won't allow EXECUTE instructions to address another EXECUTE instruction as the target instruction. Real Programmers despise petty restrictions.
并行计算机体系结构包括单指令流多数据流(SIMD)和多指令流多数据流(MIMD)两种结构。
Parallel computer architecture consists of two classifications: simple instruction stream-multiple data stream (SIMD) and multiple instruction stream-multiple data stream (MIMD).
计算机体系结构的设计思想在近四十年间发生了深刻的变化，而指令格式的设计是计算机体系结构设计的一个重要环节。
The idea of Computer architecture design has changed profoundly within the forepassed forty years, and the design of instruction format is an important part of architecture design.
我们今天不会深入到不同体系结构的特定功能。该指令适用于所有常见的硬盘。
We won't go deep into specific features of different architectures today. This instruction is common for all the drives.
本文从数据类型、指令格式与指令集合三个方面介绍一种嵌入式32位RISC微计算机的体系结构。
According to three aspects: data types, instruction formats, and instruction set, the architecture of an embedded 32 bit RISC microprocessor is introduced in this paper.
在计算机技术的许多变革中，最有意义的变革是从复杂指令集(CISC)过渡到精简指令集(RISC)体系结构。
In many revolutions of the computer techniques, the most significant one is the transmission from Complex Instruction Set computer (CISC) to Reduced Instruction Set computer (RISC) architecture.
为克服条件跳转指令的缺陷，新一代超长指令字(VLIW)体系结构的数字信号处理器(dsp)提供了对条件执行指令的支持。
As a conditional jump may cause significant code performance penalty, the architecture of recent VLIW DSPs offers support for conditional instructions.
以arm 7指令集模拟器为实例，所提出的优化技术同样适用于其它现代RISC体系结构。
An ARM7 instruction set simulator is implemented for illustration, and the optimization techniques presented in this paper are also applicable for most other modern RISC architectures.
结合ASIP体系结构特征，以应用特征为指导，针对指令集(程序代码)、流水线和存储部件进行了低功耗优化研究。
Combining with features of ASIP architecture, study on application specific low power optimization technology focusing on instruction set (program code), pipeline and storage.
这本书的用户将获得一个当代计算机体系结构的基本概念的理解，具有精简指令集计算机(RISC)的开始。
Users of this book will gain an understanding of the fundamental concepts of contemporary computer architecture, starting with a Reduced Instruction Set computer (RISC).
研究了我们自主设计的一款兼容IA-64指令集的微处理器——X处理器的体系结构，深入研究了IA-64指令集中的整数指令；
The micro-architecture of the X Processor which was designed by us and the integer instruction set of IA-64 are analyzed.
这里介绍了一种基于指令模块的主控器体系结构，它的指令集的选择依照边界扫描规范并从中提取出最基本的控制方式，具有指令扩展功能。
We practiced a special structure of a BSM based on the instruction expanded design. The instruction set was chosen carefully by studying the Boundary Scanning test standard.
本文的重点是研究基于EPIC体系结构处理器指令分支预测和整数流水线的设计与实现。
The design of branch prediction is mainly studied and the integer pipeline of processor based on EPIC architecture is designed and realized in this paper.
谓词支持是IA 6 4体系结构的新特征，它为发掘指令级并行提供了更多的机会，同时给编译器的设计者增加了难度。
Predication support is one of the new features of IA-64, which offers more opportunities for exploiting instruction level parallelism, however, brings some difficulties for compiler designers.
哈弗体系结构主要用在高速运行的系统中，所以在这些系统中缓存用来存储指令与数据是非常频繁的。
Harvard architectures tend to be targeted at higher performance systems, and so caches are nearly always used in such systems.
哈弗体系结构主要用在高速运行的系统中，所以在这些系统中缓存用来存储指令与数据是非常频繁的。
Harvard architectures tend to be targeted at higher performance systems, and so caches are nearly always used in such systems.
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