可编程脉冲延时是由EPLD来实现的。
文中讨论了基于EPLD的可编程脉冲延时单元。
In this article, a programmable pulse delay unit based on EPLD is discussed.
其它附加功能包括：可编程跳变延时、低静态电流、在轻载时提供更高的效率，以及快速关断两个驱动器的高速控制。
Additional features include: programmable transition delay, low quiescent current, higher efficiency at light loads, and high speed control to quickly turn off both gate drivers.
采用高并行度的并行延时最小均方(PDLMS)算法，用现场可编程门阵列(FPGA)实现自适应数字波束形成模块。
A new digital beam forming (DBF) method is proposed. It combines the parallel delay LMS (PDLMS) algorithm and the field programmable gate array (FPGA).
采用高并行度的并行延时最小均方(PDLMS)算法，用现场可编程门阵列(FPGA)实现自适应数字波束形成模块。
A new digital beam forming (DBF) method is proposed. It combines the parallel delay LMS (PDLMS) algorithm and the field programmable gate array (FPGA).
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