还允许虚拟机可靠地向主机机器同步它的内部时钟。
It also allows your virtual machine to reliably synchronize its internal clock to the host machine.
一般采样脉冲都是在装置内部时钟的控制下产生的。
Generally sampling pulse is produced by the control of clock inner device.
跟你的床头钟类似，你的内部时钟也是以24小时为周期的。
Similar to your bedside alarm clock, your internal clock runs on a 24-hour cycle.
他们的内部时钟从那时开始运转，使得他们能够在之后计算日期和时间。
Their internal clocks start counting from then, so they can calculate the date and time in the future.
另一个例子是设计从内部时钟获取数据的系统，用来取代请求用户输入。
Another example is designing a system that gets the date from the internal clock instead of asking for input from users.
返回计算机系统内部时钟的当前日期与时间。有关详细内容，请看“帮助”！
Returns the serial number of the current date or time. See Help for information about serial Numbers!
串行接口在内部时钟(主)模式下工作，AD 7721提供所需的串行时钟。
The serial interface operates in internal clocking (master) mode, the AD7721 providing the serial clock.
常见的始终电路设计有两种方式，一种是内部时钟方式，另一种方式为外部时钟方式。
Common always circuit design are two ways, one is internal clock way, another way to external clock way.
如果对所有组件使用相同的跟踪系统，您将被迫协调系统的多个输出，从而可能面临内部时钟不同步的风险。
If you're using the same trace system for all your components, you'll be left to tie together multiple outputs from systems with potentially unsynchronized internal clocks.
科学家很早就知道，明亮的光线可以改变大脑的内部时钟，而大脑的内部时钟则可以控制人的睡眠。
Scientist early knows, bright light can change the in-house clock of cerebrum, and the sleep that the in-house clock of cerebrum can control a person.
在传统的环境中，使用Net workTimeProtocol (ntp)守护进程保持内部时钟的精确性。
In a traditional environment, the Network Time Protocol (NTP) daemon is used to keep the internal clock accurate.
原来，当我们的内部时钟节拍加快以后，我们不但感知到外部世界的移动变慢了，我们实际上还可以记住更多的事情。
It turns out that when our internal clock is ticking faster, we don't just perceive the external world as moving slower - we can actually remember more about it.
触发源包括手动(从面板按钮)、IEEE- 488总线、TriggerLink接口、内部时钟和外部触发。
Trigger sources include manual (front panel button), IEEE-488 bus, trigger Link, internal timer, and external trigger.
时钟计数函数返回你的操作系统的内部时钟的值，并且是以毫秒的形式；它通常被用于计算总共用时，入在接下来的练习中(见图6.54)。
Tick Count (ms) returns the value of your operating system's internal clock in milliseconds; it is commonly used to calculate elapsed time, as in the next activity (see Figure 6.54).
采用一个单端时钟输入来控制所有内部转换周期。
A single-ended clock input is used to control all internal conversion cycles.
它内置一个低功耗、高速、16位不失码的采样adc、一个内部转换时钟和一个多功能串行接口。
It contains a low power, high speed, 16-bit sampling ADC with no missing codes, an internal conversion clock, and a versatile serial interface port.
内部RAM的实时时钟。
研究者们说这种电子设备除了时钟、内部存储器在维持工作，以及需要显示设置的时候，别的都处于休眠状态。
The researchers say that electronic devices are lying dormant, running their clocks, maintaining internal memories or displaying their Settings.
采用一个单时钟输入来控制所有内部转换周期。
A single clock input is used to control all internal conversion cycles.
若要确保精确，计时器应根据需要检查系统时钟，而不是尝试在内部跟踪所积累的时间。
To ensure accuracy, the timer should check the system clock as needed, rather than try to keep track of accumulated time internally.
在德克萨斯州一座偏远山峰的内部，人们正在组装一座巨型的时钟。这座钟可以在未来的一万年内计时。
INSIDE a remote mountain in Texas, a gargantuan clock is being pieced together, capable of telling the time for the next 10,000 years.
时钟电路被配置为响应于具有输入供电电压和接地电压的时钟信号向内部节点提供上拉电流。
The clocking circuit configured to provide the pull-up current to an internal node in response to a clock signal having the input supply voltage and the ground voltage.
内部会计处提供了一个快捷的开启时钟源和稳定，在不到6微秒。
The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 micro; s.
海底大地电磁仪为满足上述要求，其内部配备了高精度时钟源、姿态检测器件以及与海底电磁信息采集相关的自动信号测量与存储电路。
In order to solve the problems above, the high-precision clock, detecting posture device and automatic measurement circuit are equipped in Marine magnetotelluric instrument.
它内置一个16位高速采样adc、一个内部转换时钟、一个内部基准电压源(和缓冲)、纠错电路，以及串行和并行系统接口端口。
It contains a high speed 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports.
本发明既能完成限幅功能，又不会影响 芯片内部后续解调、稳压、时钟、复位电路的正常工作。
The invention can implement amplitude-limiting function without affecting the posterior demodulation, voltage stabilization, and normal operation of the clock and the reset circuit.
采用FPGA内部集成的FIFO模块实现像素时钟的改变和图像数据的存取。
The FIFO module in FPGA was applied to realize the pixel clock modification and the data saving and taking.
全系统采用输入数据的同步时钟作为系统时钟，系统内部采用全并行的方式，以提供灵活的速度。
The system use input clock as system clock and use parallel structure in system to provide flexible speed.
同时介绍了该分频器各级门的动态特性以及内部用三态门控制结构的优点，给出了平均延迟时间的设计结果，该设计已应用于高频时钟芯片的大批量生产中。
The dynamic performance of the gates and the advantages of internal structure of tri-state gate control are also presented. Results of the averaged time delay design are given. which have bee...
同时介绍了该分频器各级门的动态特性以及内部用三态门控制结构的优点，给出了平均延迟时间的设计结果，该设计已应用于高频时钟芯片的大批量生产中。
The dynamic performance of the gates and the advantages of internal structure of tri-state gate control are also presented. Results of the averaged time delay design are given. which have bee...
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