分析了一个异步十进制加法计数器实验电路的错误,介绍了异步十进制加法计数器典型电路。
This paper analysis the errors of experimental circuit on a asynchronous decimal carry counter, introduces a typical circuit on a asynchronous decimal carry counter.
数控分频器设计:对于一个加法计数器,装载不同的计数初始值时,会有不同频率的溢出输出信号。
Nc divider design: an adder counter, loading the initial count value, have different frequency output signal of the overflow.
数据选择器则将两个计数器中处于保持状态的奇偶数据交替输出,实现双边沿触发加法计数器的功能。
Data selector alternately to realize the functions of double edge trigger addition counter output the odd and even data in two counters.
在最近的另一项研究中,墨尔本大学的巴特沃斯博士和罗伯特·丽芙对5到6岁英语母语的儿童进行计数和简单加法进行观察。
In another recent piece of work, Dr Butterworth and Robert Reeve of the University of Melbourne watched (English-speaking) five - and six-year-olds counting and doing simple sums.
在最近的另一项研究中,墨尔本大学的巴特沃斯博士和罗伯特·丽芙对5到6岁英语母语的儿童进行计数和简单加法进行观察。
In another recent piece of work, Dr Butterworth and Robert Reeve of the University of Melbourne watched (English-speaking) five - and six-year-olds counting and doing simple sums.
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