• But, the Combinational Logic Circuits possible isn't a most simple Combinational Logic Circuits.

    但是利用逻辑函数实现的逻辑电路不一定是的逻辑电路。

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  • According to a requirement of design, the optimum parameters of combinational logic circuits can be obtained after running the program.

    根据设计要求通过程序运行获得最佳组合逻辑电路参数

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  • To stress the application of Karaugh map on designing of coding circuits in parallel-comparator ADC in terms of the design of combinational logic circuits.

    根据组合逻辑电路设计方法,突出用卡诺化简逻辑表达式并联比较型A/D转换器编码电路设计中的应用

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  • And combinational logic circuits by using VHDL language and in two ways, comparing the merits of the two implementations and different design processes and ideas.

    并且通过应用组合逻辑电路VHDL语言实现方法对照两种实现方法优劣不同设计流程和思想。

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  • In this paper the writer tries to integrate the design of asynchronos counters of arbitrary carry system with the design of combinational logic circuits in concept and method.

    本文试图把时序逻辑电路组合逻辑电路设计概念方法上统一起来。

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  • The properties of Boolean difference are made use of to derive a new method for fault testing in combinational logic circuits. This method is simpler and different from the traditional one.

    本文利用布尔差分性质,给出了一种不同于传统的求组合逻辑线路故障测试码的方法,对故障测试有一定简化作用

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  • The results of simulation prove that the improved algorithms are feasible for evolving the digital combinational logic circuits and improve the evolvable efficiency and convergence performance.

    仿真实验结果证明了改进演化算法对于实现函数级数字组合逻辑电路的硬件演化可行的,并且提高演化算法的演化效率收敛性能

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  • On the basis of the multiple-valued switch-level algebra, this paper proposes a logic design automation algorithm for NMOS and CMOS combinational circuits.

    本文开关级代数理论基础上,提出适合于NMOSCMOS组合电路的逻辑设计自动化算法

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  • This paper proposed a new algorithm of retiming which can be combined well with other combinational optimization methods to speed up logic circuits.

    提出一种改进时序重排算法使时序重排可以更有效地其他组合优化算法结合起来,共同提高同步时序电路速度

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  • This paper proposed a new algorithm of retiming which can be combined well with other combinational optimization methods to speed up logic circuits.

    提出一种改进时序重排算法使时序重排可以更有效地其他组合优化算法结合起来,共同提高同步时序电路速度

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