当器件的时钟频率，数据是转向了串行输出齐晖。
When the devices are clocked, data is shifted toward the serial output QH.
我的问题是，我怎么知道输入时钟频率应该是多少？
My question is, how do I know what the input CLK frequency should be?
Compaq服务器已经使用了几年了，CPU的时钟频率较低。
The Compaq server was a few years older, and had lower clock speed CPUs.
例如，在有些处理器上这个值可能等于处理器的时钟频率。
On some processors, for example, the count might be the cycle rate of the processor clock.
我读过的数据表，但找不到任何参考指定一个输入时钟频率。
I've read the datasheet but can't find any reference to specifying an input CLK frequency.
这是因为进程执行现在需要跨总线协调，以一半的芯片时钟频率进行处理。
This is because process execution now needs to be coordinated across the bus, which operates at half the clock frequency of the chip.
这使得能够控制复数流动的数据，甚至与相当的增加时钟频率。
This makes possible to control the plural flows of data even with the considerable increase for clock frequency.
缓存使用高速时钟频率下，缓存跟低比例的内存速度同样有用。
Use of caches At higher clock speeds, caches are useful as the memory speed is proportionally slower.
本文主要讨论我国电信网中程控交换局时钟频率维护周期的确定问题。
This article mainly addresses the maintenance period of clock frequency of SPC exchanges in China's telecommunication network.
由于反馈器件的限制，高速伪码不能采用单独依赖提高时钟频率的方法。
Because of the limits of feedback devices, high speed pseudo noise code generation cannot depend simply on the improvement of clock rate.
有一点需要注意：如果没有CPU任何活动，某些处理器会降低时钟频率。
It should be noted that some processors will step down clock speeds if there is no activity on the CPU.
时钟频率为1兆赫。在写操作的过程中，设备从传感器独处的数据总取样。
The clock frequency is 1 MHz. The device samples sensor-read data during the write operation.
就像英特尔的超高时钟频率不能在提升了，双核内存也不能让微处理器的功能增大一倍。
Just like Intel's super high clock rates don't translate into proportionately more performance, doubling of cache size certainly doesn't double the performance of a microprocessor.
给出了全相参雷达频率源的中频相干振荡源及时钟频率之间的最佳频率关系。
Best frequency relation is given between IF coherent oscillating source and clock frequency of full coherent radar.
如果需要最佳性能，必须保证晶振趋近于时钟频率，但是不能大于时钟频率。
If maximum performance is required, a crystal must be used to ensure the maximum clock frequency is approached but not exceeded.
AD7764的采样速率、滤波器转折频率和输出字速率由外部时钟频率决定。
The external clock frequency applied to the AD7764 determines the sample rate, filter corner frequencies, and output word rate.
这些系列的处理器都拥有不同的时钟频率，或者说处理器处理交给它们的指令或任务的速度。
All of those come in varying clockspeeds, or how fast a chip will perform the instructions or tasks it's given.
在这两个数据和时钟引脚不应时钟频率为减少捕获的压力和温度数据的噪音模式。
In these two modes the data and CLK pins should not be clocked to reduce noise in the captured pressure or temperature data.
问题可能出在器件的互连或工作在正常的时钟频率时集成电路就不能正常的运行了。
The problem might be an interaction between components or an IC that fails when run at normal operating clock rates.
在这种情况下，晶体振荡器就不能为设备提供稳定的时钟频率，导致设备工作异常。
In this case, the crystal oscillator can not provide a stable clock frequency, which results in the abnormality of the device.
Windows 3.x需要8086/8088或者其它时钟频率超过10MHz的处理器。
Windows 3.x required an 8086/8088 processor or better that had a clock speed of up to 10MHz.
对双核内存测评结果不是很好，但是微处理器处理速度和时钟频率或是缓存空间相比要很好的多。
Benchmark tests are not perfect, but are a better indicator of microprocessor speed than clock rate or cache size specifications.
添加并行一般通过门数增加来实现，但提高计算效率要求降低时钟频率以满足实时需求。
Adding parallelism typically increases gate count, but the improved computational efficiency allows for the lower clock frequency needed to meet real-time constraints.
因此，时钟频率直接影响单片机的速度，时钟电路的质量也直接影响单片机系统的稳定性。
Therefore, the clock frequency directly affect the speed of MCU, clocking circuit and the quality of directly influence the stability of single-chip microcomputer system.
时钟树综合是芯片后端设计至关重要的一环，时钟偏差成为限制系统时钟频率的主要因素。
Clock Tree Synthesis is important in the backend-end design of chip design, and the clock skew has become the major part of constraints that limit system clock frequency.
关键是为了使用时钟DLL，它不只是最小化时钟脉冲相位差，还提供双倍输出的时钟频率。
The trick is to use a clocked DLL, which not only minimizes clock skews, but also offers a double-frequency output clock.
这将使NVIDIA的提高，最高的时钟频率的内存，从目前的1800兆赫到2200兆赫。
This will allow NVIDIA to raise the maximum clock frequency of memory from present 1800 MHz to 2200 MHz.
假设高信号使能，计数器每个时钟周期进行计数，PWM输出的频率为时钟频率的2次幂分频。
Suppose that Enable is high, the counter counts up every clock cycle, and the frequency of the PWM output is the clock frequency divided by 2 count bits.
采样速率、滤波器转折频率和输出字速率由AD7763的外部时钟频率与配置寄存器共同设置。
The sample rate, filter corner frequencies and output word rate are set by a combination of the external clock frequency and the configuration registers of the AD7763.
采样速率、滤波器转折频率和输出字速率由AD7763的外部时钟频率与配置寄存器共同设置。
The sample rate, filter corner frequencies and output word rate are set by a combination of the external clock frequency and the configuration registers of the AD7763.
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