介绍分频锁相频率合成技术。
The technology of frequency division phase-locked frequency synthesis is introduced.
中频部分主要由HFA3724正交调制解调器和基于MB1502的锁相频率合成电路等组成。
The intermediate frequency circuit includes QPSK modulation based on HFA3724, PLL circuit based on MB1502.
在锁相频率合成器中，由于压控灵敏度的变化，环路增益也将产生同样大小的变化，这就妨碍了环路特性的最佳化。
In frequency synthesis by phase lock, the loop gain will vary by the same amount due to this effect, which generally im - pedes optimization of loop performance.
首先对直接数字频率合成技术(DDS)和锁相频率合成技术(PLL)的基本原理、特点及相噪特性作了详细的分析。
Firstly the basic theory of DDS and PLL, as well as their characteristics and phase noise properties have been analyzed detailedly.
在通信领域中，锁相环频率合成器起着越来越重要的角色。
In the field of communications, PLL synthesizers playing an increasingly important role.
采用高精度的直接数字频率合成（DDS）和数字锁相环技术，实现了高频率跟踪精度。
DDS and digital phrase-lock technology have been applied in FPGA to improve the accuracy of frequency tracking.
本文叙述了一个用微机控制的锁相环频率合成数字调谐系统的原理和设计。
In this paper the principle and design of a microcomputer-controlled PLL frequency synthesis digit tuning system is discussed.
该合成器采用程控时分复用小数分频锁相技术，解决了快速跳频频率合成中的诸多固难。
Some technique problems in fast frequency hopping synthesis are solved by making use of a programmable time division-fractional division PLL.
本文分析了数字锁相环路的寄生频偏，它是现代通讯系统中频率合成器的重要指标之一。
This paper gives an analysis of parasitic frequency deviation in the digital phase locked loop, which is one of the important specifications of modern communication systems.
锁相式频率合成技术提供了解决这一问题的思路。
Phase locked loop technique offers a way to resolve this problem.
介绍了锁相环(PLL)技术和直接数字式频率合成(DDS)技术的基本工作原理，给出了一种提高DDS输出频率精度及减小其相位截断误差的方法。
This paper introduces the theory of the phase-locked loop (PLL) and the direct digital synthesis (DDS), a method to improve the precision of DDS and reduce its phase truncation error is also given.
介绍了锁相式频率合成器的工作原理以及频率合成器关键的性能指标。
The basic working principle and the crucial parameters of phase locked synthesizer are introduced in this paper.
在锁相环频率合成器中，双模前置分频器是一个速度瓶颈。
In PLL frequency synthesizers, dual modulus prescaler is a bottleneck in achieving a higher operation speed.
锁相环频率合成器是一种相位锁定装置，是一种频率稳定度较高的离散间隔型频率信号发生器。
The phase-locked loop frequency synthesizer is a kind of phase lock installment and it is a kind of separate gap frequency code generator with high stability frequency.
锁相环路是一种能实现相位自动锁定的控制系统，主要用于频率合成及跟踪解调系统。
The phase- locked loop is one kind of control system which is able to achieve phase automatic lock, to compose frequency and to trace demodulation system.
针对一个汽车音响收音数字调谐系统的实例，介绍了一种广播用双波段锁相环频率合成芯片的设计方法。
The phase locked loop (PLL) frequency synthesizer for digital tuning system(DTS), which is used in DTS of car radio receiver, is presented.
锁相技术在调制和解调、频率合成电路等很多领域应用极其广泛。
The phase-lock technique is widely used in many fields, such as modulation and demodulation circuit and frequency synthesizer circuit.
利用锁相环的倍频、分频等频率合成技术，可以获得多频率、高稳定的振荡信号输出。
Using PLL synthesis technology such as frequency multiplication and frequency division, may obtain the multi-frequencies, the high stable oscillator signal output.
同时，建立了电荷泵锁相环频率合成器噪声模型，为高阶、低噪声电荷泵锁相环频率合成器的设计提供理论依据。
The noise model CPPLL frequency synthesizer is also established in order to provide theory of designing high order, low noise and high performance CPPLL frequency synthesizer.
在电子仪器方面，锁相环在频率合成器和相位计等仪器中起了重要作用。
In the electronic instrumentation aspect, the phase-locked loop in instruments and so on in frequency synthesizer and phase meter played the vital role.
在电子仪器方面，锁相环在频率合成器和相位计等仪器中起了重要作用。
In the electronic instrumentation aspect, the phase-locked loop in instruments and so on in frequency synthesizer and phase meter played the vital role.
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