处理器之间通过网络通讯。
图2展示了客户机应用程序与虚拟处理器之间的关系。
Figure 2 illustrates the relationship of client applications to virtual processors.
处理器之间的通信由dsp的主机接口实现。
Host Port Interface of DSP implements interprocessor communication.
SPU就像是简单的CPU设计与数字信号处理器之间的交叉。
An SPU resembles a cross between a simple CPU design and a digital signal processor.
几乎所有的传统计算机不涉及内存芯片和处理器之间的数据搬运。
Nearly everything a conventional computer doe involve chlepping data between memory chip and the proceor (or proceor, depending on the machine).
与线程池的功能类似，TPL能够在线程和处理器之间实现负载均衡。
Like a thread pool, the TPL can perform load balancing across threads and processors.
可以启动守护进程irqbalance，在处理器之间动态地分发硬件中断。
A daemon called irqbalance can be started to dynamically distribute hardware interrupts across processors.
同时，随着系统规模的不断扩大，处理器之间的通信问题变得越来越突出。
Meanwhile, with the growing of the system size, interprocessor communication overhead more and more become a bottleneck.
本发明公开了一种降低并行多数字信号处理器之间消息传递开销的方法。
The invention discloses a method for decreasing the spending of information transfer between paralleled multi-digital signal processors;
每200毫秒，调度程序就执行一次负载平衡调节，以便重新分配任务负载，维持处理器之间的平衡。
Every 200 milliseconds, the scheduler performs load balancing to redistribute the task loading to maintain a balance across the processor complex.
文中讨论了在多处理器系统上，用大规模并行处理技术实现人工神经网络时，处理器之间的通信开销问题。
The communication overhead in parallel implementation of artificial neural network on a multiprocessor system is analyzed in this paper.
此外，中间件还可以对这些缓存进行管理，从而减少主存的压力，并能在处理器之间复制这些信息，以改善工作负载管理。
In addition, the middleware can manage these caches to reduce pressure on main memory and copy them between processors to improve workload management.
通过系统中控制接口模块接收主处理器发送的控制指令，屏蔽了不同主处理器之间的差异，增强了系统的可移植性。
The control interface module shields the various differences of the main processor, which improves the portability of the coprocessor system.
但是时钟频率已经趋于饱和，现在计算机处理能力的提高主要靠增加处理器的数目以及提高在这些处理器之间分配任务的能力。
But computer clocks have plateaued and now, advances in computing power are coming from increases in the number of processors and improved abilities to distribute a problem across them.
这个小节讨论在不同的64位POWER处理器之间的兼容性，以及32位PowerPC处理器和64位POWER处理器之间的兼容性。
This section covers the compatibility between different 64-bit POWER processors. and the compatibility between the 32-bit PowerPC processor and 64-bit POWER processors.
ARINC 718a协议是ARINC 429总线协议的一部分，主要用来实现应答机和数据链路处理器之间的数据格式和通信规范的定义。
ARINC718A protocol is part of the ARINC429 bus protocol, which is mainly used to achieve definitions of data format and protocol specifications between the transponder and the data-linking processor.
这一节将介绍不同的64-位POWER处理器之间的兼容性，以及32 -位PowerPC处理器与64 -位POWER处理器之间的兼容性。
This section covers the compatibility between different 64-bit POWER processors and the compatibility between the 32-bit PowerPC processor and 64-bit POWER processors.
注意，处理器是如何基于工作负载在四个分区之间进行分配的。
Notice how the processors have been divided up between the four partitions based on workload.
这个表格包含中断与中断服务程序之间的处理器的映射，必须由程序员进行初始化。
This table contains the processor's mapping between interrupts and interrupt service routines and must be initialized by the programmer.
物理处理器将负责处理这两个线程之间的同步问题。
The physical processor takes care of synchronization issues between the two threads.
为了完成这个任务，CPU之间将要彼此通讯，从而导致每个处理器暂定当前正在运行的应用程序线程。
To do this, the CPUs will communicate with each other. This causes each processor to pause application threads that are currently running.
CMP紧密耦合的本质使处理器与内存之间的物理距离很短，因此可提供最小的内存访问延迟和更高的性能。
The tightly-coupled nature of the CMP allows very short physical distances between processors and memory and, therefore, minimal memory access latency and higher performance.
就可用性而言，这个计算系统是一个冗余设计，有两组处理器和总线，能够在主机无应答的情况下在主机和伺服机之间进行切换。
For availability, this computing system was a redundant design, with two sets of processors and buses and the ability to switch between a master and a slave if the master was found to be unresponsive.
在数据存储器和内存结构之间，有许多虚拟或后台处理器忙于处理sql语句。
Between data storage and memory structure, there are number of virtual or background processors that are busy with processing SQL statements.
图11显示出了网络流通量、磁盘活动，和处理器活动之间的趋势。
Figure 11 illustrates the trend between the network traffic, disk activity, and processor activity.
实际上，这个例子有适当的复杂性，处理器在不同操作系统之间动态分配。
In fact, this example has a nice complexity to it in that processors are being dynamically allocated between different operating systems no less!
VPA是操作系统和Hypervisor之间的一个双向通信区，用于传递所需的、有关虚拟处理器的信息。
The VPA is a two-way communication zone between the operating system and the hypervisor on information required about the virtual processor.
CBEA和Cell/B.E.处理器是Sony、Toshiba与IBM（称为STI，正式启动于 2001年初）之间协作的成果。
The CBEA and the Cell/B.E. processor are the result of a collaboration between Sony, Toshiba, and IBM, known as STI, formally started in early 2001.
SPU 与 Cell处理器的其他部件之间的主要通信方法由许多“通道”来定义。
The main communication method of the SPU with other parts of the Cell processor is defined by a number of "channels."
应用程序在有四个处理器的计算机上运行，活动线程的数量在1到8之间变化。
The application was run on a computer with four processors, and the number of active threads was varied from one to eight.
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