The invention discloses a memorizer test device based on a scan chain and a use method thereof.
本发明公开了一种基于扫描链的存储器测试装置及其使用方法。
At sometime, just one scan chain or some of the scan chains are active. Average power is reduced.
在某些时刻，仅有一个或者一部分扫描链是活跃的，从而电路的平均功耗和总功耗降低。
The invention discloses a scan chain fault diagnosis system, a method and a diagnosis vector generating device.
本发明公开了一种扫描链故障诊断系统、方法及诊断向量生成装置。
Scan chain partition improves diagnosis resolutions by solving controllability problems and observability problems.
扫描链分割技术可借由解决可控制性问题及可观察性问题来改善诊断解析度。
For a fixed set of test vectors, the overall test time can be minimized using the scan chain constructed by this method.
对于确定的测试向量集，用该方法构造的扫描链能使电路总的测试时间最少。
An optimal sequencing of the storage elements in the single scan chain design for - testability is presented in the paper.
本文提出了扫描设计中存储元件在扫描链中的最优排序方法。
For a fixed set of test vectors, the overall test time can be minimized using the scan chain constructed with this method.
对于确定的测试向量集，用该方法构造的扫描链能使电路总的测试时间最少。
Lastly, the clock speed of the bus feeding scan chain data to the pins of the DUT is increased by multiplexing the scan chain data being transferred to the bus.
最后，通过多路传送被传输到总线的扫描链数据，可以提高输送扫描链数据到DUT管脚的总线的时钟速度。
A scan test scheme based on scan chain disabling technique has been proposed, which can effectively reduce test power. However, its test application time is long.
一种基于扫描链阻塞技术的扫描测试结构被提出来，该结构有效地降低了测试功耗，但其测试应用时间较长。
For the test application time can be reduced effectively, this paper proposes an approach based on scan chain disabling technique, in view of incompatible test vector compression method.
为进一步降低测试功耗及测试应用时间，提出一种基于扫描链阻塞技术且针对非相容测试向量的压缩方法。
To resolve them, two design methods of board level dynamic BS chain based on boundary scan technology are proposed in this paper.
为了解决上述问题，文中提出了两种基于边界扫描技术的板级动态链路设计方法。
To resolve them, two design methods of board level dynamic BS chain based on boundary scan technology are proposed in this paper.
为了解决上述问题，文中提出了两种基于边界扫描技术的板级动态链路设计方法。
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