Based on the analysis of the complexity and hardware architecture of FFT, the proposed processor adopts radix-4 DIF algorithm, pipelined architecture and fixed-point operation.
在分析了FFT算法的复杂度和硬件实现结构的基础上，处理器采用了按频率抽取的基- 4算法，分级流水线以及定点运算结构。
This design adopts the algorithm of radix-4 and decimation-in-time (DIT) to devise a real-time FFT hardware processor with practicality.
设计采用基4算法设计了一个具有实用价值的FFT实时硬件处理器。
In this multiplier, modified radix 4 booth encoding algorithm is used to reduce the number of partial products by half.
在这个乘法器中，采用了修正过的4基数展位编码算法来将部分乘积减少到一半。
In accordance with the requirements of high speed digital signal processing, the algorithm of radix-4 implemented with FPGA and the integrated architecture and butterfly unit are analyzed.
给出了频域抽取二维向量基快速傅里叶变换算法，针对二维频域信号采用频域抽取方法，导出了该快速算法蝶形运算的一般形式并给出了算法实现流程图。
In accordance with the requirements of high speed digital signal processing, the algorithm of radix-4 implemented with FPGA and the integrated architecture and butterfly unit are analyzed.
给出了频域抽取二维向量基快速傅里叶变换算法，针对二维频域信号采用频域抽取方法，导出了该快速算法蝶形运算的一般形式并给出了算法实现流程图。
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