Logic for interface to the back-side bus for accesses to the internal unified level two processor cache.
访问内部统一二级处理器缓存的后端总线接口逻辑。
When a thread exits a synchronized block as part of releasing the associated monitor, the JMM requires that the local processor cache be flushed to main memory.
当线程为释放相关监视器而退出一个同步块时，J MM要求本地处理器缓冲刷新到主存中。
Under heavy system loads, specifying which processor should run a specific thread can improve performance by reducing the number of times the processor cache is reloaded.
在高系统负载的情况下，指定该由那个处理器执行特定的执行绪，可以减少重新载入处理器快取的次数，因而增进效能。
A positive note: the XSL processor cache does not need to be flushed; XSL processors with associated style sheets can be used until the style sheets change, which typically does not occur at run time.
正面评价：不必清除XSL处理器缓存。与样式表关联的XSL处理器可以一直使用到样式表改变为止，但样式表的更改一般不会在运行时发生。
If a program reads a single byte in memory, the processor loads the whole cache line that contains that byte into the L2 and L1 caches.
如果一个程序在存储中读到一个单独的字节，处理器就会释放包含字节的所有的缓存线到L2和L1缓存中。
When a program writes to memory, the processor only modifies the line in the cache, but does not update main memory.
当一个程序写入存储，处理器仅仅只会修改缓存线，而不会更新主要的存储内容。
Objects are ultimately stored in memory, but the compiler, runtime, processor, or cache may take some liberties with the timing of moving values to or from a variable's assigned memory location.
对象最终存储在内存中，但编译器、运行库、处理器或缓存可以有特权定时地在变量的指定内存位置存入或取出变量值。
The processor might perform dozens or hundreds of operations on a chunk of data in the cache before relinquishing it to memory.
处理器可能会在将一个数据块交还给内存前对这块数据执行数十或数百次操作。
First, the processor checks an image cache to see if the image is preloaded or has been recently used.
首先，处理器检查图像缓存，看图像是否已预先加载，或者最近使用过。
This leads to various inefficiencies, especially loss of low-level cache contents when moving to a new processor with a cold cache.
这会导致多种效率低下，尤其是当低级缓存内容迁移到具有冷缓存的新处理器时会丢失低级缓存内容。
Each processor also has its own fast memory (a level 1 cache).
每个处理器也拥有自身的快速内存(1级缓存)。
The cache implemented by the ESI processor is an in-memory cache.
ESI处理器实现的缓存是内存内缓存。
Linux attempts to execute a thread on the same processor for cache performance reasons.
出于缓存性能的原因，Linux尝试在同一个处理程序中执行线程。
The snippet processor checks the cache before accessing the disk.
snippet处理器在访问磁盘之前检查缓存。
The Web server plug-in contains a built-in ESI processor which caches whole pages, as well as fragments, providing a higher cache hit ratio.
Web服务器插件包含内置ESI处理器，该处理器将缓存整个页以及必要的片段，具有较高的缓存命中率。
To speed up address translation, there is a processor-on-a-chip (PoC) cache and associated logic called translation lookaside buffer (TLB).
为了加快地址转换，架构中有一个 processor-on-a-chip (PoC)缓存和相关的转换后备缓冲器 (TLB)逻辑。
Processor: % Processor Time not over 80% longer then 10 min. (add or upgrade CPU's - preferably with large level2 cache like 2mb).
Processor： % ProcessorTime不超过10min的80%(添加或升级CPU—最好带有大容量level2缓存，比如2mb)。
I-cache miss (Processor cannot get the next instruction from instruction cache).
I -cache失效(处理器无法从指令缓存获取下一个指令)。
The profiling table provides the percentage and number of samples collected for specified processor events such as the number of cache line misses, Transition Lookaside Buffer (TLB) misses, and so on.
评测表提供为特定的处理器事件收集的采样的百分数或数量，比如高速缓存线路故障的数量、传输后备缓存(TLB)故障的数量，等等。
More data is passed to the cache and processor; this is somewhat analogous to the improvement that broadband connections offer over dial-up connections.
更多的数据被传递到高速缓存和处理器中；这就像相对于拨号连接，宽带连接的进步一样。
If a D-cache miss (the processor fails to find data in the D-cache) occurs, an interrupt is raised so that the corresponding register can record this event by increasing its value.
如果发生D -cache失效(处理器无法在D - cache中找到数据)，那么发出一个中断，让相应的寄存器可以通过增加它的值记录这一事件。
Time-based cache attacks analyzes the time difference in the execution of algorithm over a processor, and recovers the secret key.
基于时间的缓存攻击是指通过分析处理器中算法的不同执行时间来恢复密钥的攻击。
Without getting too technical, the new A-series APUs are made using a 32nm manufacturing process and each processor core on the "CPU side" of the APU has 1mb of its own Level 2 cache.
没有得到太多的技术，新的A系列的APU使用32纳米的制造工艺和每个处理器核心上的“CPU侧”的APU拥有自己的二级缓存1MB。
This is done to improve scalability by making better use of the local cache for each processor on a multiprocessor system.
这在多处理器系统上，有利于各个处理器更好的使用本地缓存，提高扩展性。
The base system consists of a 375mhz processor with 4mb of ECC (error checking and correcting) Level 2 (L2) cache.
基础系统包括一个375mhz处理器，带有4MB的ECC(错误检查和纠正)2级(二级)缓存。
The target processor can access data in the cache more efficiently than it accesses data in the system memory.
目标处理器能够比访问系统存储器中的数据更有效率地访问高速缓存中的数据。
The target processor can access data in the cache more efficiently than it accesses data in the system memory.
目标处理器能够比访问系统存储器中的数据更有效率地访问高速缓存中的数据。
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