Other devices are not memory mapped on the processor bus.
其他的设备没有被映射到处理机总线上。
The high contention rate of the processor bus becomes a performance bottleneck.
对处理器总线的高争夺率成为性能瓶项。
A bidirectional multidrop processor bus is connected to a plurality of bus agents.
一条双向多点处理器总线连接到多个总线代理。
The NUMA architecture can increase processor speed without increasing the load on the processor bus.
NUMA体系结构可以在不增加处理器总线负载的情况下提高处理器速度。
To carry out a fetch, the processor places the binary-code address of the desired location onto the address lines of the external processor bus.
为了便于获取指令，处理器把需要的由二元数据构成的地址存储在外部处理机总线的序列里面。
The internal processor bus described in Sec. XX is connected to the external processor bus by a set of bus buffers located on the microprocessor integrated circuit.
XX节所描述的内部总线通过一组位于微处理器集成电路内的总线缓冲器与外部总线连接。
As more and more processors are added to the server, the processor bus can become a performance bottleneck as it attempts to handle instructions across different resources.
随着越来越多的处理器添加到服务器，处理器总线将成为性能瓶颈，因为它试图处理跨不同资源的指令。
The address bus is used by the processor to select aspecific memory location or register within a particular peripheral.
地址总线被处理器用来选择在特定外设中的存储器地址或寄存器。
A BMC links to a main processor and other on-board elements using a simple serial bus.
BMC利用简单的串行总线与主处理器和板上其他部件相连。
The processor is connected to physical memory by the memory bus.
处理器通过内存总线连接到物理内存。
In a typical microarchitecture, a processor has its bus turned on even when it is not in use.
在传统的微体系结构中，即使总线不在使用中，处理器也会将其打开。
With the Pentium m processor and Celeron m processor, portions of the bus are turned on only when they are needed.
但奔腾M处理器和赛扬m处理器只会在需要时才打开总线的某些部分。
This paper introduces the protocol of FPDP bus and the design of FPDP bus of general signal processing boards with TS-101 processor.
本文介绍FPDP总线的通信协议和基于TS-101处理器的通用信号处理板的板间FPDP总线通信方式的设计与实现。
As an external interface of the processor, system bus component affects the efficiency of memory system directly.
作为处理器的片外接口，系统总线部件直接影响着存储系统的效能。
ARINC718A protocol is part of the ARINC429 bus protocol, which is mainly used to achieve definitions of data format and protocol specifications between the transponder and the data-linking processor.
ARINC 718a协议是ARINC 429总线协议的一部分，主要用来实现应答机和数据链路处理器之间的数据格式和通信规范的定义。
We study the split transaction pipelining technology in detail, and apply it to the implementation of system bus component in X processor.
本文详细研究了这种分离事务流水执行技术并应用该技术实现了X处理器系统总线部件。
The opening structure of the STD BUS managed by a Z80 processor helps to build up a flexible and expansible data acquisition system.
由Z80微处理器管理的STD总线开放式结构具有灵活地扩充、方便地获取数据等特点。
To IXP1200 Network Processor, receiving packet and transmitting packet are finished by Receive State Machine and transmit State Machine in IX bus separately.
在微引擎中的包的接收和转发是通过利用IX总线接口单元的接收状态机和转发状态机来完成的。
This design and implementation of a double modular. fault-tolerant computer sys-tem interfacing to STD-BUS is presented for the industrial process oriented processor withhigh reliability.
本文论述STD 总线双机容错系统的设计与实现，该系统为工矿企业提供高可靠性的处理机模块。
Logic for interface to the back-side bus for accesses to the internal unified level two processor cache.
访问内部统一二级处理器缓存的后端总线接口逻辑。
The opening structure of the STD BUS managed by a Z80 processor helps to build up a flexible and expansible data acquisiti…
由Z80微处理器管理的STD总线开放式结构具有灵活地扩充、方便地获取数据等特点。
The address bus is used by the processor to select a specific memory location or register within a particular peripheral.
地址总线被处理器用来选择在特定外设中的存储器地址或寄存器。
A host controller transfers data over a bus communication system, under the control of a processor, in individual transactions.
一种主机控制器在处理器的控制下经由总线通信系统在单独事务中传送数据。
The bus and the processor core often run in different clock frequencies, so their interface signals belong to different clock domains.
总线时钟与处理器内核时钟频率不同，因此总线部件与处理器内核间的接口信号需要进行时钟域转换。
Because of their advantages, CAN bus becomes the most capable bus, and DSP becomes one of the best choices of smart device's processor.
由于自身优势，CAN总线成为最有可能的总线结构，而DSP芯片成为智能器件处理器的好选择。
The power-optimized processor system bus remains powered down until it senses incoming data form the chipset, allowing to the processor to consume less power.
电源优化的处理器系统总线始终处于断电状态，直到感知来自芯片组的数据才通电，从而减少处理器的耗电量。
With the development of fabricate technology for digital signal processor (DSP), the power dissipation of the bus is the main part of the wh ole power dissipation in DSP.
随着数字信号处理器制造工艺的进步，总线的功耗已经成为数字信号处理器功耗的主要组成部分。
This system with the control core of 80c552 single chip processor adopts bus isolation technique, realizing the time-sharing processing of high-speed data collecting and data processing.
该系统以80c552单片机为控制核心，采用总线隔离技术，实现高速数据采集与数据处理分时进行。
The intersection controller is based on STD bus structure, its processor adopting MSC-89C51 monolithic computers of the INTEL company.
下位机的路口信号机基于STD总线结构，处理器采用了INTEL公司的MSC-89C51单片计算机。
The intersection controller is based on STD bus structure, its processor adopting MSC-89C51 monolithic computers of the INTEL company.
下位机的路口信号机基于STD总线结构，处理器采用了INTEL公司的MSC-89C51单片计算机。
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