The router arithmetic of the parallel processor is complex. The circuit has long latency and the logic has the huge size.

并行处理器互连网络的路由算法异常复杂，电路延迟长，逻辑规模巨大，是制约高性能并行处理器提高频率、降低功耗的瓶颈。

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This paper presents a multiple fault test simulator for sequential logic circuit. The simulator is implemented in serial-parallel to save memory.

本文给出一个时序逻辑电路的多故障测试模拟程序。

youdao

This paper presents a multiple fault test simulator for sequential logic circuit. The simulator is implemented in serial-parallel to save memory.

本文给出一个时序逻辑电路的多故障测试模拟程序。

youdao