If the data or instruction is not present in the cache, or if the cache line is invalidated, the CPU updates its cache by reading the data from the main memory.
如果数据或指令没有出现在高速缓存中，或者如果高速缓存线路无效的时候，CPU通过从主存储器中读数据来更新它的高速缓存。
Neither a memory management unit nor an instruction or data cache are used.
这既不需要使用内存管理单元，也不需要使用指令或数据缓存。
The most common analysis is data dependence analysis, which is to determine the instructions that use the variable (register or memory location) modified by another instruction.
最通常的分析是数据依存性分析，它用来确定指令使用的变量(寄存器或内存位置)是否被另一条指令修改。
The CPU reads and interprets the instructions, reads the data required by each instruction, executes the action required by the instruction, and stores the results back in memory.
CPU读取并解释指令，读取每一条指令所需的数据，执行指令所需的动作并将结果存储回内存。
Program instruction set, logic stack and data type of I/O memory which are tied up with tasks in the soft-PLC system are analyzed and studied.
研究了系统的程序指令集、逻辑堆栈和I/O存储器数据类型，实验表明系统具有良好的实时性和可靠性。
In some systems, there is much more instruction memory than data memory so instruction addresses are wider than data addresses.
在一些系统中，指令存储器比数据存储器更大，所以指令地址的宽度要高达数据地址。
In a computer with the contrasting von Neumann architecture (and no CPU cache), the CPU can be either reading an instruction or reading/writing data fROM/to the memory.
在基于冯诺依曼架构的计算机中（没有CPU缓存），CPU或者从存储器中读取指令或数据，或者在存储器中写入数据。
Memory is a function of direct access to central processing instruction and data memory.
内存是中央处理机能直接存取指令和数据的存储器。
An instruction where each parameter is independent of the others, for example, when moving data from memory to a floating-point register.
一条指令，其中每一个参数与其它参数无关，例如，把数据从存储器。
In a computer using the Harvard architecture, the CPU can both read an instruction and perform a data memory access at the same time, even without a cache.
在使用哈佛架构的计算机中，即使没有缓存，CPU也可以在读取指令的同时进行数据访问。
Another unique architectural feature is the memory system which allows an instruction fetch and at the same time a data access by each individual core at every single clock cycle.
另一个独特的构架特性是内存系统，它允许一个取指，并在同一时间，每一个核可以读取数据在每一个单独的时钟周期内。
Another unique architectural feature is the memory system which allows an instruction fetch and at the same time a data access by each individual core at every single clock cycle.
另一个独特的构架特性是内存系统，它允许一个取指，并在同一时间，每一个核可以读取数据在每一个单独的时钟周期内。
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